Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu, "Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices", Proc. of the 30th Asia and South Pacific Design Automation Conference (ASP-DAC'25), pp.xxx-xxx, Jan 2025. (to appear)

Man Wu and Masaaki Kondo, "A High-Throughput Network Intrusion Detection System Using On-Device Learning on FPGA", The 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2024), Dec. 2024.

Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, and Masaaki Kondo, "DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference",  2024 Design, Automation and Test in Europe Conference (DATE 2024), March 2024. (DOI: 10.23919/DATE58400.2024.10546578)

Shaswot Shresthamali and Masaaki Kondo, "Enhancing Deep Reinforcement Learning with Compressed Sensing-based State Estimation", The 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), Dec. 2023. 

Junfeng Wu, Yuan He, Masaaki Kondo, "Accelerating Graph-Based SLAM through Data Parallelism and Mixed Precision on FPGAs", The 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), Dec. 2023. 

Junyuan Zheng, Yuan He, Masaaki Kondo, "Exploiting Data Parallelism in Graph-Based Simultaneous Localization and Mapping: A Case Study with GPU Accelerations'', The International Conference on High Performance Computing in Asia-Pacific Region 2023 (HPC Asia 2023), pp.126-139, March 2023 (DOI: https://doi.org/10.1145/3578178.3578237).

Shaswot Shresthamali, Yuan He, and Masaaki Kondo, "FAWS: Fault-Aware Weight Scheduler for DNN computations in heterogeneous and faulty hardware", The 20th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2022 ), Dec. 2022.

Jun Zhou and Masaaki Kondo, "Interactive and Reliable Graph Processing via the Edge-Cloud Collaboration Framework", The 24th IEEE International Conference on  High Performance Computing and Communications (HPCC-2022), Dec. 2022.

Man Wu, Hiroki Matsutani, and Masaaki Kondo, "ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC", The 24th IEEE International Conference on  High Performance Computing and Communications (HPCC-2022), Dec. 2022.

Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He, and Masaaki Kondo", Memory Bandwidth Conservation for SpMV Kernels through Adaptive Lossy Data Compression" The 23rd International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT’22), Dec. 2022.

Ryuichi Sakamoto, Yuriko Ezaki, Masaaki Kondo , "Hash Distributed A* on an FPGA", 2022 International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2022), pp. 76–83, June 2022.

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi, "QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery", The 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA-28), pp.274-287, April 2022.

 Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, and Hiroshi Nakamura, "GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications", The 30th International Conference on Parallel, Distributed and Network-Based Processing (PDP 2022), March 2022.

Shaswot Shresthamali, Masaaki Kondo, and Hiroshi Nakamura, "Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes", The IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), pp.98-105, Dec. 2021.

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi, "QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code", 58th ACM/EDAC/IEEE Design Automation Conference (DAC2021), Dec. 2021.

Yang Qin and Masaaki Kondo, "Federated Learning-Based Network Intrusion Detection with a Feature Selection Approach", Third International Conference on Electrical, Communication and Computer Engineering (ICECCE 2021),  June 2021.

Hiroki Oikawa and Masaaki Kondo, "Density-Based Data Selection and Management for Edge Computing", 2021 IEEE International Conference on Pervasive Computing and Communications (PerCom2021), March 2021.

Yuan He, Jinyu Jiao and Masaaki Kondo, "Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks", 29th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2021), March 2021.

Motoki Sakurai, Yosuke Ueno, Masaaki Kondo, "Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing", 2021 IEEE International Conference on Intelligence and Safety for Robotics (IEEEISR 2021), March 2021.

Yang Qin, Hiroki Mastutani, and Masaaki Kondo, "A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection", 13th International Conference on Cyber, Physical and Social Computing (CPSCom-2020), pp.178-185, Oct. 2020.

Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, and Masaaki Kondo, "Fast Semi-supervised Anomaly Detection of Drivers’Behavior using Online Sequential Extreme Learning Machine",  The 23rd IEEE Intelligent Transportation Systems Conference (ITS2020), 8-pages, Sep. 2020.

Yuan He, Jinyu Jiao, Thang Cao and Masaaki Kondo, "Energy-Efficient On-Chip Networks through Profiled Hybrid Switching", The 30th ACM Great Lakes Symposium on VLSI (GLSVLSI 2020), pp241-246, Sep. 2020.

Ryuichi Sakamoto, Masaaki Kondo, Kohei Fujita, Tsuyoshi Ichimura, and Kengo Nakajima, The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption, International Conference on High Performance Computing in Asia Pacific Region (HPCAsia 2020), pp.199–206, Jan. 2020.

Shaswot Shresthamali, Masaaki Kondo, and Hiroshi Nakamura, "Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning", The 37th IEEE International Conference on Computer Design (ICCD2019), pp.638-647, Nov. 2019.

Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo and Mitaro Namiki, "A Preliminary Evaluation of Buiding Block Computing Systems", 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.312-319, Oct. 2019.

Rei Ito, Mineto Tsukada, Masaaki Kondo Hiroki Matsutani, "An Adaptive Abnormal Behavior Detection using Online Sequential Learning", Proc. of the 17th International Conference on Embedded and Ubiquitous Computing (EUC'19), Aug 2019.

Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector", The 16th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'18), Aug. 2018.

Ryuichi Sakamoto, Tapasya Patki, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Daniel Ellsworth, Barry Rountree, and Martin Schulz, "Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers", 32nd IEEE International Parallel & Distributed Processing Symposium (IPDPS2018), 10pages, May 2018.

Yasutaka Wada, Yuan He, Thang Cao, Masaaki Kondo, "A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems", SupercomputingAsia 2018 (SCA18), 20pages, Mar. 2018.

Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, "The Design and Implementation of Scalable Deep Neural Network Accelerator Cores", IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), 8pages, Sep. 2017.

Ryuichi Sakamoto, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Tapasya Patki, Daniel Ellsworth, Barry Rountree, and Martin Schulz, "Production Hardware Overprovisioning: Real-world Performance Optimization using an Extensible Power-aware Resource Management Framework", 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS2017). 10pages, May 2017.

Thang Cao, Wei Huang, Yuan He, and Masaaki Kondo, "Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems", 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS2017), 10pages, May 2017.

Tetsui Ohkubo, Ryo Tanaka, Ryuichi Sakamoto, Masaaki Kondo, and Hideharu Amano, "NAMACHA: A Software Development Environment for a Multi-Chip Convolutional Network Accelerator", 32nd International Conference on Computers and Their Applications (CATA'17), Mar. 2017.

Yuan He and Masaaki Kondo, "Opportunistic Circuit-Switching for Energy Efficient On-Chip Networks", The 24th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2016), 6pages, Sep. 2016.

Thang Cao, Yuan He, and Masaaki Kondo, "Demand-Aware Power Management for Power-Constrained HPC Systems", The 16th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid2016), pp.21-31, May 2016.

Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, and Ikuo Miyoshi, "Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing", The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15), 12pages, Nov. 2015.

Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura, "Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections", The 33rd IEEE International Conference on Computer Design (ICCD2015), pp.455-458, Oct. 2015.

Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, and Koji Inoue, "A Flexible Hardware Barrier Mechanism for Many-Core Processors", 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), pp.61-68, Jan. 2015.

Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, "Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating", International Symposium on System-on-Chip 2014, Oct. 2014.

Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda and Hiroshi Nakamura, "Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors", Design, Automation and Test in Europe Conference and Exhibition (DATE2014), 6pages, Mar. 2014.

Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, "Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors", 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014). pp.843-848, Jan. 2014.

Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo and Hiroshi Nakamura, "Demonstration of a Hetero- geneous Multi-Core Processor with 3-D Inductive Coupling Links", 23rd International Conference on Field Programmable Logic and Applications (FPL2013), Demo Presentations, Sep. 2013.

Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namik, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura, "Dynamic Power Control with a Heterogeneous Multi-Core System Using a 3-D Wireless Inductive Coupling Interconnect", 2012 International Conference on Field-Programmable Technology (FPT2012), Demo Session, pp.293-296, Dec. 2012.

Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, "Cool Mega Array: a highly energy efficient reconfigurable accelerator", International Conference on Field-Programmable Technologies (FPT 2011), pp.1-8, Dec. 2011. 

Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu. Amano, Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura, "Adaptive Power Gating for Function Units in a Microprocessor", 11th IEEE International Symposium on Quality Electronic Design (ISQED-2010), pp.29-37, March 2010.

Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo, "Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating", IEEE Asian Solid-State Circuits Conference 2009 (A-SSCC 2009), pp.281-284, Nov. 2009. 

Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura, "Cooperative Shared Resource Access Control for Low-Power Chip Multiprocessors", 14th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-2009), pp.177-182, Aug. 2009. 

Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitustaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, and Hiroshi  Nakamura, "Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression", The 22nd IEEE International Conference on VLSI Design, pp.381-386, Jan. 2009. 

Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitustaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo and Hiroshi Nakamura, "A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000", XXVI International Conference on Computer Design (ICCD-2008), pp.612-617, Oct. 2008. 

Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, "Power Reduction of Chip Multi-Processors using Shared Resource Control Cooperating with DVFS", XXV International Conference on Computer Design (ICCD-2007), pp.615-622, Oct. 2007. 

Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "An Intra-Task DVFS Technique based on Statistical Analysis of Hardware Events", International Conference on Computing Frontiers 2007 (CF 2007), pp.123-130, May 2007. 

Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, "Task Scheduling under Performance Constrations for Reducing Energy Consumption of GALS Multi-Processor SoC", Design Automation and Test in Europe 2007 (DATE 2007), April 2007. 

Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping", International Symposium on Low Power Electronics and Design 2006 (ISLPED 2006), pp.43-48, Oct. 2006. 

Masaaki Kondo and Hiroshi Nakamura, "Small, Fast and Low-Power Register File by Bit-Partitioning", 11th International Symposium on High-Performance Computer Architecture (HPCA 2005), pp.40-49, Feb. 2005.

Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, and Takashi Nanya, "Skewed Checkpointing for Tolerating Multi-Node Failures", 23rd Symposium on Reliable and Distributed Systems (SRDS 2004), pp.116-125, Oct. 2004. 

Taku Ohneda, Masaaki Kondo, Masashi Imai, and Hiroshi Nakamura, "Design and Evaluation of High Performance Microprocessor with Reconfigurable On-Chip Memory", 2002 Asia-Pacific Conference on Circuits and Systems (APCCAS 2002), pp.211-216, October 2002. 

Masaaki Kondo, Mitsugu Iwamoto, and Hiroshi Nakamura, "Cache Line Impact on 3D PDE Solvers", 4th International Symposium on High Performance Computing (ISHPC 2002), LNCS 2327, pp.301-309, May 2002. 

Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, and Taisuke Boku, "SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing", 2000 International Conference on Computer Design (ICCD 2000), pp.105-111, Oct. 2000.

Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku, and Shuichi Sakai, "SCIMA: A Novel Processor Architecture for High Performance Computing", HPC-Asia 2000, pp.355-360, May 2000.

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, "Body Bias Control on a CGRA based on Convex Optimization", IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 25), April 2022.

Jun Zhou and Masaaki Kondo, "Lightweight Interactive Graph Processing Library for Edge Computing in Smart Society", 14th International Workshop on Autonomous Self-Organizing Networks (ASON'21 ) in conjunction with CANDAR'21, Nov. 2021.

Yunjiao Ma, Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, and Masaaki Kondo, "Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL",  9th International Workshop on Computer Systems and Architectures (CSA'20) in conjunction with CANDAR'21, Nov. 2021.

Yuetsu Kodama, Masaaki Kondo and Mitsuhisa Sato, "Evaluation of SPEC CPU and SPEC OMP on A64FX",  Third annual Energy Efficient High Performance Computing State of the Practice Workshop  (EE HPC SOP), Sep. 2021.

Ryohei Tomura, Takuya Kojima, Hideharu Amano, Ryuichi Sakamoto, and Masaki Kondo, "A Real Chip Evaluation of a CNN Accelerator SNACC", The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies, Oct. 2019.

Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), April 2013.

Takefumi Miyoshi，Keigo Shima，Masaaki Kondo，Hidetsugu Irie, Hiroki Honda，and Tsutomu Yoshinaga, "FLAT: A GPU Programming Framework to Provide Embedded MPI", 5th Workshop on General Purpose Processing on Graphics Processing Units (GPGPU 2012), pp. 20-29，March 2012.

Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, "SLD-1(Silent Large Datapath)：A Ultra Low Power Reconfigurable Accelerator", IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), April 2011. 

Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami, Tetsuya Sunata, Kazuki Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo, "Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating", IEEE Symposium on Low-Power and High-Speed Chips, (COOL Chips XIII), April 2010. 

Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, and Hiroshi Nakamura, "Power-Performance Modeling of Heterogeneous Cluster-Based Web Servers", Energy Efficient Grids, Clouds and Clusters Workshop (E2GC2), Oct. 2009.

Toshiya. Komoda, Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "Compiler Directed Fine Grain Power Gating for Leakage　Power Reduction in Microprocessor Functional Units", 7th Workshop on Optimizations for DSP and Embedded Systems (ODES-2009), March 2009.

Masaaki Kondo，Yoshimichi Ikeda, and Hiroshi Nakamura, "A High Performance Cluster System Design by Adaptive Power Control"，Workshop on High-Performance Power-Aware Computing (HPPAC 2007), March 2007. 

Masaaki Kondo, Hiroshi Sasaki, and Hiroshi Nakamura, "Improving Fairness, Throughput and Energy-Efficiency on a Chip Multiprocessor through DVFS", Workshop on Design, Architecture and Simulation of Chip Multi-Processors 2006 (dasCMP 2006) , Dec. 2006.

Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, "Dynamic Instruction Cascading on GALS Microprocessor", International Workshop on Power And Timing Modeling, Optimization and Simulation 2005 (PATMOS 2005), LNCS 3728, pp30-39, Sep. 2005.

Masaaki Kondo and Hiroshi Nakamura, "Dynamic Processor Throttling for Power Efficient Computations", Workshop on Power-Aware Computer Systems 2004 (PACS 2004), LNCS 3471, pp120-134, Dec. 2004. 

Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, and Mitsuhisa Sato, "SCIMA-SMP: On-chip Memory Processor Architecture for SMP", 3rd workshop on Memory performance issues, ACM Electronic Edition, pp. 121-128, June 2004. 

Motonobu Fujita, Masaaki Kondo, and Hiroshi Nakamura, "Data Movement Optimization for Software-Controlled On-Chip Memory", 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT 2004), pp.120-127, Feb. 2004. 

Masaaki Kondo, Shinichi Tanaka, Motonobu Fujita, Hiroshi Nakamura, "Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory", Workshop on Compilers and Operating Systems for Low Power, (COLP 2002), Sep. 2002. 

Hiroshi Nakamura, Masaaki Kondo, and Taisuke Boku, "Software Controlled Reconfigurable On-Chip Memory for High Performance Computing", 2nd International Workshop on Intelligent Memory Systems, LNCS 2107, pp.15-32, 2000. 

Jun Zhou and Masaaki Kondo, "Imperceptible Trojan Attacks to the Graph-based Big Data Processing in Smart Society", IEICE Transactions on Information and Systems, Vol. E108-D, No.1, pp.-, Jan. 2025 (In-Press).

Yuri Alexeev, et. al., "Quantum-centric supercomputing for materials science: A perspective on challenges and future directions", Future Generation Computer Systems, Vol. 160, pp.666-710, Nov. 2024, (doi: https://doi.org/10.1016/j.future.2024.04.060).

Jun Zhou and Masaaki Kondo, "An Edge-Cloud Collaboration Framework for Graph Processing in Smart Society", IEEE Transactions on Emerging Topics in Computing, Vol. 11, No. 4, pp.985-1001, Oct.-Dec. 2023 (doi: 10.1109/TETC.2023.3297066).

Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He, Masaaki Kondo, and Hiroshi Nakamura, "Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV",  IEICE Transactions on Information and Systems, Vol. E106-D, No.12, pp.2015-2025, Dec. 2023.

Kazuki Sunaga, Masaaki Kondo, and Hiroki Matsutani, "Addressing Gap between Training Data and Deployed Environment by On-Device Learning",  IEEE Micro,  Vol. 43, No.6, Nov. 2023 (doi: 10.1109/MM.2023.3314711).

 Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, and Hiroshi Nakamura, "An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications",  Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Vol.102, No.104895, pp.1-12, Oct. 2023 (doi: https://doi.org/10.1016/j.micpro.2023.104895).

Yuetsu Kodama, Masaaki Kondo and Mitsuhisa Sato, "Evaluation of Performance and Power Consumption on Supercomputer  Fugaku using SPEC HPC benchmarks", IEICE Transactions on Electronics, Vol. E106-C, No.6, June 2023.

Jun Zhou and Masaaki Kondo, "An Interactive and Reductive Graph Processing Library for Edge Computing in Smart Society",  IEICE Transactions on Information and Systems, Vol.E106-D, No.3, pp.319-327,  March 2023. 

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “A Scalable Body Bias Optimization Method Towards Low-Power CGRAs”, IEEE Micro, Vol. 43, no. 1, pp. 49-57, Jan.-Feb. 2023. DOI: 10.1109/MM.2022.3226739. [Early Access]

Jinyu Jiao, Yuan He, Thang Cao, Masaaki Kondo, "Enabling circuit-switching in modern on-chip networks", Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Oct. 2022 (https://doi.org/10.1016/j.micpro.2022.104712) .

Shaswot Shresthamali, Masaaki Kondo, and Hiroshi Nakamura, "Multi-Objective Resource Scheduling for IoT Systems Using Reinforcement Learning", Journal of Low Power Electronics and Applications, Vol. 12, Issue. 4, Oct. 2022 (DOI: https://doi.org/10.3390/jlpea12040053). [pdf (Open Access)]

Yiyu Tan, Toshiyuki Imamura, and Masaaki Kondo, “FPGA-Based Acceleration of FDTD Sound Field Rendering”, Journal  of Audio Engineering Society, vol. 69, no. 7/8, pp. 542–556, July/August, 2021 (DOI: https://doi.org/10.17743/jaes.2021.0025). 

Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Guanqin Pan, Thang Cao, and Masaaki Kondo, "Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems",  IEICE Transactions on Electronics, Vol.E104-C, No.6,  pp.237-246, June 2021.

Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "A Neural Network-Based On-device Learning Anomaly Detector for Edge Devices", IEEE Transactions on Computers (TC), Vol.69 Issue 7, pp.1027-1044, July 2020. [pdf (Open Access)] 

塚田 峰登, 近藤 正章, 松谷 宏紀, "OSUAD: FPGAを用いたオンライン逐次学習型教師無し異常検知器", 情報処理学会論文誌コンピューティングシステム (ACS65), Vol.12, No.3, pp.34-45, 2019年7月.

Shaswot Shresthamali, Masaaki Kondo, and Hiroshi Nakamura, "Adaptive Power Management in Solar Energy Harvesting Sensor Node using Reinforcement Learning", ACM Transactions on Embedded Computing Systems, Vol.16, No.5s, pp.181:1-181:21, Oct. 2017.

Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura, "A Runtime Multi-Optimization Framework to Realize Energy Efficient Networks-on-Chip", IEICE Transactions on Information and Systems, Vol.E99-D, No.12, pp.2881-2890, Dec. 2016.

Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, and Mitaro Namiki, "An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications", IEICE Transactions on Electronics, Vol.E99-C, No.8, pp.926-935, Aug. 2016.

Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, and Mitaro Namiki, "A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units", IEICE Transactions on Electronics, Vol.E98-C, No.7, pp.559-568, July 2015.

和田 康孝, 近藤 正章, 本多 弘樹, "粗粒度な電圧ドメインを持つメニーコアプロセッサ向け低消費電力化タスクスケジューリング", 情報処理学会論文誌コンピューティングシステム(ACS), Vol.8, No.1, pp.34-50, 2015年3月.

島 圭吾, 吉見 真聡, 三好 健文, 近藤 正章, 入江 英嗣, 本多 弘樹, 吉永 努, "FLAT: MPIを 埋め込み可能なGPUプログラミングフレームワーク", 情報処理学会論文誌コンピューティングシステム, Vol.6, No.4, pp.105-116, 2013年10月.

Son Truong Nguyen, Masaaki Kondo, Tomoya Hirao, and Koji Inoue, "A Prototype System for Many-core Architecture SMYLEref with FPGA Evaluation Boards", IEICE Transactions on Information and Systems, Vol.E96-D, No.8, pp.1645-1653, Aug. 2013. 

Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki, "Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design", IEICE Transactions on Electronics (INVITED PAPER), Vol.E96-C, No.4, pp.404-412, April 2013.

Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, "Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips", IEEE MICRO Magazine, Vol.31, No.6, Dec. 2011.

薦田 登志矢, 佐々木 広, 近藤 正章, 中村 宏, "細粒度な空き時間を利用したコンパイラによるリーク電力削減手法", 情報処理学会論文誌 コンピューティングシステム（ACS）, Vol.4, No.4, pp.36-50, 2011年11月.

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano, "Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units", IPSJ Transactions on System LSI Design Methodology, Vol.4, No., pp.182-192, Aug. 2011.

佐々木 広, 高木 紀子, 近藤 正章, 中村 宏, "共有資源の競合を考慮したチップマルチプロセッサ向け低消費電力化手法", 情報処理学会論文誌 コンピューティングシステム（ACS）, Vol.4, No.2, pp.40-58, 2011年3月. 

関 直臣, レイ ジャオ, 小島 悠, 池淵 大輔, 長谷川 揚平, 大久保 直昭, 武田 晴大, 香嶋 俊裕, 白井 利明, 宇佐美 公良, 砂田 徹也, 金井 遵, 並木 美太郎, 近藤 正章, 中村 宏, 天野 英晴, "MIPS R3000プロセッサにおける細粒度動的スリープ制御の実装と評価", 電子情報通信学会論文誌, Vol.J93-D No.6, pp.920-930, 2010年6月. 

近藤 正章, 高木 紀子, 中村 宏, "Pipeline Blocking：走行時パワーゲーティングのための命令実行制御手法", 情報処理学会論文誌 コンピューティングシステム（ACS）, Vol.2, No.3, pp.83-95, 2009年9月.

Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping", IEEE Transactions on VLSI (Transactions Briefs), Vol.17 Issue 6, pp. 848-852, June 2009.

近藤 正章, 佐々木 広, 中村 宏, "トラクションコントロール実行：CMP向けプロセス実行制御方式の提案", 情報処理学会論文誌 コンピューティングシステム（ACS）, Vol.1, No.2, pp.111-123, 2008年8月. 

大谷 貴胤, 佐々木 広, 近藤 正章, 中村 宏, "モデリングに基づくWebサーバ用計算機クラスタの低消費電力化", 情報処理学会論文誌 コンピューティングシステム（ACS）, Vol.1, No.1, pp.120-132, 2008年6月. 

金井 遵, 佐々木 広, 近藤 正章, 中村 宏, 天野 英晴, 宇佐美 公良, 並木 美太郎, "性能予測モデルの学習と実行時性能最適化機構を有する省電力化スケジューラ", 情報処理学会論文誌 Vol.49, No.SIG2(ACS21), pp.20-36, 2008年3月. 

近藤 正章, 中村 宏, "CMP向け動的電源電圧・周波数制御手法", 情報処理学会論文誌 Vol.48, No.SIG13(ACS19), pp.260-269, 2007年8月. 

Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya, "Design Method of High Performance and Low Power Functional Units Considering Delay Variations", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No. 12, pp.3519-3528, Dec. 2006.

佐々木 広, 浅井 雅司, 池田 佳路, 近藤 正章, 中村 宏, "統計処理に基づく動的電源電圧制御手法", 情報処理学会論文誌, Vol.47, No.SIG18 (ACS 16), pp.80-91, 2006年11月. 

池田 佳路, 近藤 正章, 中村 宏, "実効電力制御による高性能計算機クラスタ構成手法の提案", 情報処理学会論文誌, Vol.47, No.SIG12 (ACS 15), pp.262-271, 2006年9月. 

東 美和子, 近藤 正章, 今井 雅, 中村 宏, 南谷 崇, "空間的に故障率が異なる計算機クラスタシステムにおけるチェックポインティング", 電子情報通信学会論文誌 Vol.J98-D No.8, pp.1705-1716, 2006年8月. 

近藤 正章, 中村 宏, "ビット分割構成によるレジスタファイルのサイズおよびポート数削減手法", 情報処理学会論文誌 Vol.46, No.SIG12(ACS11), pp. 62-72, 2005年8月. 

藤田 元信, 近藤 正章, 中村 宏, "ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法", 情報処理学会論文誌, Vol.45, No.SIG11(ACS7), pp. 219-228, 2004年10月. 

近藤 正章, 中村 宏, "主記憶アクセスの負荷情報を利用した動的周波数変更による低消費電力化", 情報処理学会論文誌, Vol. 45, No. SIG 6(ACS 6), pp.1-11, 2004年5月. 

藤田 元信, 近藤 正章, 中村 宏, "ソフトウェア制御オンチップメモリ向け自動最適化コンパイラの提案", 情報処理学会論文誌, Vol.45, No. SIG(ACS4), pp.77-87, 2004年1月. 

Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, and Atsushi Hori, "Evaluation of Checkpointing Mechanism on SCore Cluster System", IEICE Transactions on Information and Systems, Vol.E86-D, No.12, Dec. 2003.

Masaaki Kondo and Hiroshi Nakamura, "Reducing Memory System Energy by Software-Controlled On-Chip Memory", IEICE Transactions on Electronics, Vol.E86-C, No. 4, pp.550-588, April 2003.

高橋 睦史, 近藤 正章, 朴 泰祐, 高橋 大介, 中村 宏, 佐藤 三久, "HPC向けオンチップメモリプロセッサアーキテクチャSCIMAのSMP化の検討と性能評価", 情報処理学会論文誌, Vol.44, No.SIG6(ACS1), 2003年4月.

近藤 正章, 中村 宏, 朴 泰祐, "SCIMAにおける性能最適化手法の検討", 情報処理 学会論文誌, Vol.42, No.SIG 12(HPS 4), pp.37-48,2001年11月. 

板倉 憲一, 早川 秀利, 近藤 正章, 吉川 茂洋, 朴 泰祐, 田中 良夫, 佐藤 三久, "メモリバスアクセス率に基づくSMP-PCクラスタの性能評価", 情報処理学会論文誌, Vol. 41, No. SIG 5(HPS 1), pp.70-79, 2000年8月. 

中村 宏, 近藤 正章, 大河原 英喜, 朴 泰祐, "ハイパフォーマンスコンピューティング向けアーキテクチャSCIMA", 情報処理学会論文誌, Vol. 41, No. SIG 5(HPS 1), pp.15-27, 2000年8月. 

呉 漫, FPGA上での軽量オンデバイス学習を用いた高帯域ネットワーク侵入検知手法", 情報処理学会研究報告 システム・アーキテクチャ，2023-ARC-251()，2023年8月．

Shresthamali Shaswot and Masaaki Kondo，"Enhancing Deep Reinforcement Learning with Compressed Sensing-based State Estimation"，情報処理学会研究報告 システム・アーキテクチャ，2023-ARC-251()，2023年8月．

多賀 直史，上野洋典，近藤正章, "量子ビットの誤り率の偏りを考慮したニューラルネットワークによる量子誤り訂正手法の検討", 情報処理学会研究報告 システム・アーキテクチャ，2023-ARC-251()，2023年8月．

立間凌，和遠，近藤正章，"PIMアーキテクチャにおけるメモリバンク間のデータ送受信機構の検討", 情報処理学会研究報告 システム・アーキテクチャ，2023-ARC-251()，2023年8月．

マオ イーカイ, シュレスタマリ サソット, 近藤正章, "LSTMネットワークを用いたNISC向け量子回路の忠実度向上手法", 情報処理学会研究報告 量子ソフトウェア, 2023年6月. 

上杉太郎，ソニーノ ロレンツォ，近藤正章，"SRAMインメモリ計算を用いた近似デジタル乗算器の精度向上の検討"，情報処理学会研究報告 システム・アーキテクチャ，2022-ARC-249(47)，2023年3月．

倉垣勇介，和遠，近藤正章，"SRAMベースProcessing-in-Memory計算アクセラレータ向けのコマンドセット拡張の検討"，情報処理学会研究報告 システム・アーキテクチャ，2023-ARC-252(46)，2023年3月．

杉本寛直，シュレスタマリ サソット，近藤正章，"局所グラフ情報を用いた強化学習によるAGVの経路スケジューリング手法の検討"，電子情報通信学会技術報告，CPSY2022-49, pp.89-94, 2023年3月．

Shaswot Shresthamali, Yuan He, Masaak Kondo, "Fault-aware Hardware Scheduling of Computations in Deep Neural Networks", 情報処理学会研究報告 システム・アーキテクチャ，2022-ARC-249(19)，2022年7月．

ソニーノ ロレンツォ，シュレスタマリ サソット，和遠，近藤正章，"DNN推論高速化のためのSRAMベース近似デジタル乗算器の提案", 情報処理学会研究報告 システム・アーキテクチャ，2022-ARC-249(16)，2022年7月．

塚田峰登，近藤正章，松谷宏紀，"無線センサノードを対象としたオンデバイス学習の異常検知への応用"，電子情報通信学会技術報告，CPSY2022-10，pp.53-58，2022年7月．

児玉祐悦, 近藤正章, 佐藤三久，"富岳におけるSPEC HPCの評価"，情報処理学会研究報告 ハイパフォーマンスコンピューティング，2022-HPC-185(13)，2022年7月． 

瀧下 創 , 和 遠 , 近藤 正章 , 天野 英晴, "Graph-Based SLAMのFPGAによる高速化の検討", 電子情報通信学会技術報告, CPSY2021 (62), pp.103-108, 2022年3月.

小畠 晟裕, 上野 洋典, 近藤 正章, "ニューラルネットワークを用いた量子誤り訂正手法の改良の検討", 情報処理学会研究報告 システム・アーキテクチャ, 2022-ARC-248 (39), 2022年3月.

胡 思已 , 伊藤 真紀子 , 吉川 隆英 , 近藤 正章, "メモリアクセス時データ精度変換機構によるSpMV処理の高速化の検討", 情報処理学会研究報告システム・アーキテクチャ, 2022-ARC-248(42), 2022年3月.